Flexibility

For rapid custom signal development, HLS compatible interface is provided to 10 levels of orderbook as well as market trade messages. Running example code is provided. For example, below is a very simple trade size signal that simply returns the quantity traded with a sign convention indicating which side of the trade was the aggressor.

Any such signal can be used to release accelerated orders to the market with a wire-to-wire tick-to-trade latency that cannot be beaten using a pure software solution. The strategy smarts remain in software to provide desired strategy update speed and flexibility.

Obviously signals can also be implemented in VHDL and Verilog.

void process_trade_size(
        uint64_t *timestamp,
        uint32_t *seqnum,
        uint16_t *angelia_id,
        uint16_t *signal_id,
        uint32_t *exch_id,
        uint8_t *display_factor_idx,
        uint8_t *exponent,
        uint64_t *price,
        uint32_t *qty,
        uint16_t *numords,
        uint2 *side,
        volatile axi_stream_data64_t *signal_id_out,
        volatile axi_stream_data64_t *signal_value_out,
        volatile axi_stream_data64_t *signal_seqnum_out,
        volatile axi_stream_data64_t tx_trade_crunched[184] 
        )
{
#pragma HLS PIPELINE off
#pragma HLS INTERFACE ap_ctrl_none port = return
#pragma HLS INTERFACE ap_vld register port=timestamp
#pragma HLS INTERFACE ap_vld register port=seqnum
#pragma HLS INTERFACE ap_vld register port=angelia_id
#pragma HLS INTERFACE ap_vld register port=signal_id
#pragma HLS INTERFACE ap_vld register port=exch_id
#pragma HLS INTERFACE ap_vld register port=display_factor_idx
#pragma HLS INTERFACE ap_vld register port=exponent
#pragma HLS INTERFACE ap_vld register port=price
#pragma HLS INTERFACE ap_vld register port=qty
#pragma HLS INTERFACE ap_vld register port=numords
#pragma HLS INTERFACE ap_vld register port=side

#pragma HLS INTERFACE axis register both depth=64 port=signal_id_out
#pragma HLS INTERFACE axis register both depth=64 port=signal_value_out
#pragma HLS INTERFACE axis register both depth=64 port=signal_seqnum_out
#pragma HLS INTERFACE axis register both depth=184 port=tx_trade_crunched
    axi_writer_t axi_rpt_writer;
    axi_writer_t_initialise(&axi_rpt_writer, tx_trade_crunched);

    axi_writer_t axi_signal_id_writer;
    axi_writer_t_initialise(&axi_signal_id_writer, signal_id_out);

    axi_writer_t axi_signal_value_writer;
    axi_writer_t_initialise(&axi_signal_value_writer, signal_value_out);

    axi_writer_t axi_signal_seqnum_writer;
    axi_writer_t_initialise(&axi_signal_seqnum_writer, signal_seqnum_out);

    msg_signal_type_t signal_type = msg_signal_trade_size;


    if(*signal_id && *side > 0 ) {
        int64_t value = *side == 1 ? *qty : -(int64_t)*qty;

        axi_writer_t_write64_direct_commit(&axi_signal_id_writer,  *signal_id);
        axi_writer_t_write64_direct_commit(&axi_signal_value_writer,  value);
        axi_writer_t_write64_direct_commit(&axi_signal_seqnum_writer,  *seqnum);

        msg_signal_t_write(&axi_rpt_writer, *angelia_id, *signal_id, *exponent, *display_factor_idx, signal_type, value, *seqnum);
    }
}